1. Field of the Invention
The present invention relates to a semiconductor device including a transistor.
2. Description of the Related Art
A thin film transistor (TFT) is formed using a thin semiconductor layer.
As a method for achieving high performance of a semiconductor device, there is a method which achieves high definition in a semiconductor device. A smaller contact hole is necessary in order to achieve high definition in a semiconductor device.
In order to achieve high performance in a semiconductor device, there is another method in which a channel formation region of a semiconductor layer included in a semiconductor device is thinned.
There is a technology in which increase in field-effect mobility, improvement in a field-effect subthreshold property, and reduction in leak current can be achieved by thinning a channel formation region of a semiconductor layer.
A channel formation region, a source region, and a drain region of a thin film transistor are formed using the identical semiconductor film in many cases.
In such a case, when the channel formation region of the thin film transistor is thinned, the source and drain regions are also thinned unintentionally.
Consequently, in forming contact holes, a problem is more likely to arise that the semiconductor layer is removed entirely by overetching.
In view of the above problem, Reference 1 (Japanese Published Patent Application No. H5-13762) discloses an etching method for achieving both a smaller contact hole and prevention of overetching.